The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2000
Filed:
Nov. 17, 1998
Kazumi Kita, Tokyo, JP;
Advantest Corporation, Tokyo, JP;
Abstract
In a variable delay circuit calibrating method in which the state of connection of M delay stages connected in cascade through multiplexers and weighted differently is controlled by a control signal value to generate a calibrated amount of delay corresponding to a nominal amount of delay D.sub.s which varies in a predetermined minimum nominal delay step d.sub.s, the method comprises the steps of: dividing an amount of delay D.sub.i measured for each given control signal value CC.sub.i by the minimum nominal delay step d.sub.s of a variable delay circuit; calculating first and second errors, R.sub.k =D.sub.i -d.sub.s k and R.sub.k+1 =d.sub.s -R.sub.k, between the value k of an integral part of the resulting quotient and two adjoining nominal amounts of delay D.sub.sk and D.sub.sk+1 ; making a check to determine if the first error R.sub.k is smaller than an error held in a k-th row of a calibration table in correspondence with a nominal set signal value CS=k; if so, writing the first error R.sub.k and the corresponding control signal value CC.sub.i over the existing values in the column of the k-th row of the calibration table; making a check to determine if the second error R.sub.k+1 is smaller than an error held in a (k+1)-th row of the calibration table in correspondence with a nominal setting signal value CS=k+1; and, if so, writing the second error R.sub.k+1 and the corresponding control signal value CC.sub.i over the existing values in the column of the (k+1)-th row of the calibration table. By repeatedly executing these steps for i=0 to i=2.sup.M -1, control signal values, which minimize errors between delay times of the variable delay circuit and the nominal amounts of delay, are generated in O-th to K-th rows of the calibration table in correspondence with the respective nominal setting signal values CS.
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