Voltage level transfer

Abstract

A single-end-input voltage level transfer is provided to transfer a first signal into a second signal. The voltage level transfer has a first, a second, a third, and a fourth transistors, a first inverter, and a second inverter, in which the first transistor is an NMOS transistor and the other three are PMOS transistors. A first transistor source is coupled to the first signal. An input end of the first inverter is coupled to a first transistor drain. An output end of the first inverter is coupled to an input end of the second inverter, which exports the second signal. A second transistor source is coupled to a first power source, and a second transistor drain is coupled to a first transistor gate. A second transistor gate is controlled by a complementary second signal. A third transistor source is coupled to a second power source, and a third transistor drain is coupled to the first transistor gate. A third transistor gate is controlled by the second signal. A second transistor substrate and a third transistor substrate are coupled to the second power source. A fourth transistor source is coupled to the second power source. A fourth transistor drain is coupled to first transistor drain. A fourth transistor gate is coupled to the complementary second signal.