The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 19, 2000
Filed:
Dec. 09, 1998
Bai Nguyen, San Jose, CA (US);
Om P Agrawal, Los Altos, CA (US);
Bradley A Sharpe-Geisler, San Jose, CA (US);
Jack T Wong, Fremont, CA (US);
Herman M Chang, Cupertino, CA (US);
Vantis Corporation, Sunnyvale, CA (US);
Abstract
A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the array of plural interconnect resources. The array of plural interconnect resources does not regularly include lines of single-length or shorter, and the array of plural interconnect resources does not regularly include switchbox areas that are spaced apart from one another by distances of a single-length or shorter. The single-length corresponds to a traverse of a continuous distance covering approximately one VGB.