Integration of a diffusion barrier layer and a counter dopant region to

Abstract

An integrated circuit fabrication process is provided for placing a diffusion barrier layer above the junctions of a transistor and counter dopant regions at the boundaries of the junctions to enhance the dopant level within the junctions. The diffusion barrier layer (e.g., a nitride layer) is strategically placed between the junctions and sidewall spacers which extend laterally from the opposed sidewall surfaces of a gate conductor. The diffusion barrier layer inhibits the dopants within the junctions from passing into the sidewall spacers. Dopant species opposite in type to those in the junctions are implanted into the counter dopant regions using a 'large tilt angle' (LTA) implant methodology, wherein the angle of incidence of the injected dopant ions is at a non-perpendicular angle relative to the upper surface of the semiconductor substrate. In this manner, the counter dopant regions are placed both beneath the junctions and at the juncture between the junctions and the channel region of the transistor. The counter dopants fill vacancy and interstitial sites within the substrate, and thus block migration avenues through which the dopants in the junctions could otherwise pass into other areas of the substrate. The integration of the diffusion barrier layer with the counter dopant regions ensures that the dopant concentration within the junctions will be maintained.