The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2000

Filed:

Oct. 27, 1998
Applicant:
Inventor:

Adrianus W Ludikhuize, Eindhoven, NL;

Assignee:

U. S. Phillips Corporation, New York, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257549 ; 257343 ; 257492 ; 257544 ;
Abstract

The invention relates to a half-bridge circuit comprising two series-connected n-channel DMOS transistors, in which the source of the one transistor, the low-side transistor T.sub.1, is connected to a low-voltage terminal V.sub.ss, and the drain of the other transistor, the high-side transistor T.sub.2, is connected to a high-voltage terminal V.sub.dd. The drain of the low-side transistor and the source of the high-side transistor are connected to the output terminal (4). The circuit is arranged in a semiconductor body having an n-type or p-type epitaxial layer (11) which is applied to a p-type substrate (10). In the epitaxial layer, two n-type regions are defined for the transistors, each of said regions forming a drift region of one of the transistors and being surrounded by a cup-shaped n-type zone in the semiconductor body. Within the n-type cup-shaped zone (12) of the low-side transistor T.sub.1, there is provided a p-type cup-shaped zone which isolates the drift region (15) of T.sub.1 from the cup-shaped zone (12) and which is connected, along with the cup-shaped zone (12), the backgate region (17) and the source (19) of T.sub.1, to V.sub.ss. In the high-side transistor, the n-type cup-shaped region (13) is connected, together with the drain, to V.sub.dd. As in the case of the low-side transistor, the n-type cup-shaped zone is at a fixed voltage, it is precluded that electrons are injected by this zone into the substrate, and, consequently, also the risk of latch-up and disturbances in the rest of the circuit is precluded. It is also precluded that, at a higher resistivity of the substrate, voltage jumps occur in the substrate, which could also give rise to latch-up and disturbances. In addition, at least the low-side transistor can be constructed in such a manner that the RESURF condition is met, thus enabling the device to be used also at a high voltage.


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