The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2000
Filed:
Jul. 02, 1998
Applicant:
Inventors:
Masaaki Higashitani, Sunnyvale, CA (US);
Hao Fang, Cupertino, CA (US);
Narbeh Derhacobian, Belmont, CA (US);
Assignees:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Fujitsu Limited, , JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
438257 ; 438976 ; 438275 ; 438258 ; 438266 ;
Abstract
An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.