System and method for aligning output signals in massively parallel

Abstract

Signal alignment circuitry aligns (i.e., deskews) test signals from a massively parallel tester. A timing portion of each signal is received by a rising edge delay element, a falling edge delay element, and a transition detector, all in parallel. The delay of the rising edge and falling edge delay elements is independently controlled by control circuitry. The outputs of the rising edge and falling edge delay elements are muxed together, and the output of the flux is selected in response to rising edge and falling edge transitions detected by the transition detector. The output of the mux is provided to pulse generating circuitry, which generates a pulse at each edge for use in clocking a data portion of each signal into a DQ flip-flop. The output of this DQ flip-flop is then latched in to another DQ flip-flop by a reference clock. To control the rising and falling edges of one of the test signals, and thereby align the signal with the other test signals, the control circuitry first sweeps the delay in the rising edge and falling edge delay elements until the latched-in signal transitions. Then, the reference clock is delayed by a known amount of time, and the delay in the rising edge and falling edge delay elements is again swept until the latched-in signal transitions. This provides enough information to characterize delay functions of the rising edges and falling edges of the signal in terms of a point-slope formula, which, in turn, allows for complete control over the rising and falling edges of the signal and for the alignment of the signal with the other signals.