Microcomputer having memory and processor formed on the same chip to

Abstract

A first memory of a large storage capacity is connected to a DQ pad for inputting and outputting an information signal through a bus interface unit. A first bidirectional transfer circuit and a second bidirectional transfer circuit for bidirectionally transmitting an information signal are provided between a high-speed memory and the memory of the large storage capacity. The first bidirectional transfer circuit is connected with the large storage capacity memory through a common bus, and the high-speed memory is interconnected with the second transfer circuit through a fifth bus. This second bidirectional transfer circuit is connected to an instruction register and a data register through a sixth bus. A processor is arranged in proximity to this instruction register and the data register, so that the processor processes an instruction from the instruction register and data from the data register and stores a processing result in the data register again. The bus interface unit is interconnected with the DQ pad through a first bus, and interconnected with the mass storage capacity memory through the second bus. The first and second bidirectional transfer circuits are interconnected with each other through a fourth bus. By arranging the respective buses independently of each other respectively, the processor can execute processing internally through an available bus during information signal transmission in an exterior.