The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2000

Filed:

Dec. 30, 1997
Applicant:
Inventors:

Robert W Horst, Saratoga, CA (US);

William Edward Baker, Austin, TX (US);

Linda Ellen Zalzala, Austin, TX (US);

William Patterson Bunton, Austin, TX (US);

Richard W Cutts, Jr, Georgetown, TX (US);

David J Garcia, Los Gatos, CA (US);

John C Krause, Georgetown, TX (US);

Stephen G Low, Austin, TX (US);

David Paul Sonnier, Austin, TX (US);

William Joel Watson, Austin, TX (US);

Patracia L Whiteside, Austin, TX (US);

Assignee:

Tandem Computer Incorporated, Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; H04L / ;
U.S. Cl.
CPC ...
710 19 ; 370236 ; 370506 ; 709232 ; 714-4 ; 714 10 ;
Abstract

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.


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