The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2000

Filed:

Apr. 22, 1999
Applicant:
Inventors:

George McNeil Lattimore, Austin, TX (US);

Donald George Mikan, Jr, Austin, TX (US);

Binta Minesh Patel, Round Rock, TX (US);

Gus Wai-Yan Yeung, Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 83 ; 326 81 ; 326 17 ; 327534 ;
Abstract

A silicon-on-insulator digital circuit combination having a body voltage control stage and a voltage clamp stage. The body voltage control stage is responsive to an input control signal to provide an output driver signal. The body voltage control stage has a first transistor with a terminal for electrically-coupling to a combinational logic circuit, and a body contact electrically-coupled to the input control signal such that a threshold voltage of the transistor is reduced when the transistor is placed in an active state. It can be readily appreciated that the reduced threshold voltage of the transistor increases the transition rate for the first transistor to an inactive state in response to the input control signal. The voltage clamp stage has a second transistor responsive to the input control signal such that the terminal is electrically-coupled to a reference voltage when the first transistor is in the inactive state.


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