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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6154808 B1

PDFFull Text
Date of Patent:
Nov. 28, 2000

Filed:

May. 19, 1998

Method and apparatus for controlling data erase operations of a

Applicant:
Inventors:

Takeshi Nagase, Yokohama, JP;

Shinpei Komatsu, Yokohama, JP;

Yoshihiro Takamatsuya, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:

Staas & Halsey LLP

Primary Examiner:

John W Cabeca

Assistant Examiner:

Pierre-Michel Bataille

Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711103 ; 711166 ; 36518529 ;
Abstract

A semiconductor memory device has a memory space which includes blocks and each of the blocks includes sectors. The sectors have a data storing region and a flag region. Data stored in a sector is marked as valid or erased, depending on the flags in the flag region. If an even number of the flags in the flag region have a logical value of 1, the data is considered to be erased. The data in each sector may be erased and unerased a number of times, by sequentially altering the value of the flags in the flag region. Data stored in the memory may be erased on a sector-by-sector basis.

Find Patent Forward Citations

Nagase, Takeshi. (2000). Method and apparatus for controlling data erase operations of a (U.S. Patent No. 6154808). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6154808

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