Semiconductor memory device with a column redundancy occupying a less

Abstract

A semiconductor memory device is provided which comprises a mat having a plurality of sectors for storing information of data; and a redundancy circuit for generating a plurality of redundancy selection signals to be applied in common to the sectors when the enable fuse element is open-circuited. Each of the sectors comprises a main memory cell array plural input/output blocks, each of which corresponds to the input/output pins and has two bit and the redundancy memory cell array divided into two redundant bit segments, each of which has two redundant columns of redundant memory cells. Each sector further comprises a first column selector for selecting one of the main columns of each bit segment in response to first column address signals; a second column selector for selecting one of the two redundant columns of each redundant bit segment in response to one of the first column address signals; and a third column selector for selecting one of the two bit segments in each input/output block and one of the two redundant bit segments in response to second column address signals. Furthermore, each sector has a plurality of sense amplifiers for sensing and amplifying stored data in corresponding main column and redundant column thus selected; and a plurality of multiplexers each for receiving outputs from a first corresponding sense amplifier and from the second sense amplifier and selecting one of the outputs thus received in response to a corresponding redundancy selection signal.