The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2000

Filed:

Apr. 24, 1996
Applicant:
Inventors:

Christopher Harris, Sollentuna, SE;

Ulf Gustafsson, Linkoping, SE;

Mietek Bakowski, Skultuna, SE;

Assignee:

ABB Research Ltd., Zurich, CH;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257 78 ; 257213 ; 257 57 ; 257 58 ; 257 59 ; 257291 ; 257294 ; 257326 ; 257347 ; 257360 ; 257363 ; 257401 ; 257153 ; 257341 ; 257147 ; 438268 ; 438546 ; 438931 ; 438272 ; 438274 ; 438545 ;
Abstract

A transistor of SiC having a drain and a highly doped substrate layer is formed on the drain. A highly n type buffer layer may optionally be formed on the substrate layer. A low doped n-type drift layer, a p-type base layer, a high doped n-type source region layer and a source are formed on the substrate layer. An insulating layer with a gate electrode is arranged on top of the base layer and extends substantially laterally from at least the source region layer to a n-type layer. When a voltage is applied to the gate electrode, a conducting inversion channel is formed extending substantially laterally in the base layer at an interface of the p-type base layer and the insulating layer. The p-type base layer is low doped in a region next to the interface to the insulating layer at which the inversion channel is formed and highly doped in a region thereunder next to the drift layer.


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