The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2000

Filed:

Aug. 28, 1997
Applicant:
Inventors:

Mark Stanley Papamarcos, San Jose, CA (US);

Andrew Jefferson Read, Sunnyvale, CA (US);

Wayne Phillip Heideman, San Jose, CA (US);

Robert Kristianto Mardjuki, Peasanton, CA (US);

Robert Kimberly Couch, Santa Cruz, CA (US);

Peter Ralph Jaeger, San Jose, CA (US);

William Fitch Kappauf, San Jose, CA (US);

Melvin Rudin, Los Altso, CA (US);

Norman Francis Kelly, San Jose, CA (US);

Lawrence Curtis Widdoes, Jr, Los Altos Hill, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; H01R / ;
U.S. Cl.
CPC ...
703 13 ; 439490 ;
Abstract

An improved system or and method of connecting a hardware modeling element to the pin electronics circuitry of a hardware modeling system, with the improved system having circuitry and structures that will allow it to be connected to a hardware modeling system that is powered, circuitry to indicate to the pin electronics circuitry that the improved system is connected to it, circuitry to identify the hardware modeling element supported by the improved system to the hardware modeling system, circuitry to indicate to the hardware modeling system when the hardware modeling element is initialized so evaluation of it by the hardware modeling system can commence, circuitry to generate selectable supply voltages for the powering the hardware modeling element, and a hardware modeling element connector that will allow the connection of a family of hardware modeling elements to the same connector without the need to change the connector.


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