The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2000
Filed:
Jun. 03, 1997
Wei Edwin Wu, Austin, TX (US);
Hsing-Huang Tseng, Austin, TX (US);
Phillip Earl Crabtree, Austin, TX (US);
Yeong-Jyh Tom Lii, Austin, TX (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains.