The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2000
Filed:
Sep. 25, 1997
Katsura Hayashi, Kokubu, JP;
Akihiko Nishimoto, Kokubu, JP;
Yukihiro Hiramatsu, Kokubu, JP;
Yuji Iino, Kokubu, JP;
Shuichi Tateno, Kokubu, JP;
Riichi Sasamori, Kokubu, JP;
Shigeaki Fukumoto, Kokubu, JP;
Kyocera Corporation, Kyoto, JP;
Abstract
A multilayer wiring board formed by laminating a plurality of circuit board units each including an insulating board containing at least a thermosetting resin, and a wiring circuit layer formed on the surface of said insulating board, wherein said insulating board is provided with via hole conducting passages so as to electrically connect the wiring circuit layers of the neighboring circuit board units, said via hole conducting passages are formed by filling via holes formed in the insulating board with a conducting paste, and said wiring circuit layer is buried in the surface of the insulating board in a manner that said insulating board possesses a flat surface. The multilayer wiring board has a satisfactory flatness required for mounting flip chips. Besides, the insulating board and the via hole conducting passages are not infiltrated by chemicals such as etching solution or plating solution. There is no problem of defective circuit, and connection is highly reliably maintained offering advantage in realizing a highly dense wiring.