The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2000

Filed:

Feb. 19, 1999
Applicant:
Inventor:

Peter Breger, Calabasas, CA (US);

Assignee:

Teradyne, Inc., Boston, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 56 ; 326 56 ; 326 57 ; 326 59 ; 326 60 ; 326 33 ; 326127 ;
Abstract

A tristate circuit for driving three signal levels to a pin of a device-under-test is disclosed. The tristate circuit includes a driver having an output at a first signal level and adapted for coupling to the pin. A first switching unit couples to the output and responds to a programmed signal. The first switching unit operates to selectively alter the first signal level to a second signal level. A second switching unit connects serially to the first switch. The second switching unit responds to a second programmed signal and operates to cooperate with the first switch to alter the second signal level to a third signal level.


Find Patent Forward Citations

Breger, Peter. (2000). Serial switch driver architecture for automatic test equipment (U.S. Patent No. 6137310). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6137310

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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