The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2000
Filed:
Apr. 30, 1999
Gayle W Miller, Colorado Springs, CO (US);
Gail D Shelton, Colorado Springs, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of fabricating a semiconductor wafer is disclosed. The method includes the steps of (i) doping a resist substance with an electromagnetic radiation absorbing compound so as to form an electromagnetic radiation absorbing resist material, (ii) forming an electromagnetic radiation absorbing resist layer on a first side of the semiconductor wafer with the electromagnetic radiation absorbing material, (iii) subjecting the first side of the semiconductor wafer to an electromagnetic signal so that an amount of the electromagnetic signal is absorbed by the electromagnetic radiation absorbing compound present in the electromagnetic radiation absorbing resist layer such that an attenuated electromagnetic signal emanates from the semiconductor wafer, (iv) etching the first side of the semiconductor wafer during the subjecting step in order to remove a quantity of the electromagnetic radiation absorbing resist layer from the first side of the semiconductor wafer, (v) determining an intensity level of the attenuated electromagnetic signal, and (vi) stopping the etching step in response to the intensity level of the attenuated electromagnetic signal having a predetermined relationship with an intensity threshold level. An associated arrangement for etching a first side of a semiconductor wafer down to a desired level is also disclosed.