Programmable divider circuit with a tri-state inverter

Abstract

A programmable dividing circuit comprises a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages being configured so that when an output of the last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages. The circuit includes a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and wherein the second plurality M of transistor stages includes at least some of said first plurality N of transistor stages, including said first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the circuit operates as a divide-by-M circuit in which an output signal is generated which has one cycle for every M cycles of a clock signal applied to the transistor stages. The circuit includes a switching circuit having at least two inputs and arranged to selectively connect to the first stage, the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.