The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2000
Filed:
Apr. 27, 1998
Applicant:
Inventors:
Albert Chan, Palo Alto, CA (US);
Ju Shen, San Jose, CA (US);
Cyrus Y Tsui, Los Altos, CA (US);
Allan T Davidson, San Jose, CA (US);
Assignee:
Lattice Semiconductor Corp., San Jose, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 41 ; 326 93 ; 326101 ;
Abstract
A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portions of the programmable logic device.