The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2000
Filed:
Nov. 24, 1999
Ritu Shrivastava, Fremont, CA (US);
Chitranjan N Reddy, Los Altos Hills, CA (US);
Alliance Semiconductor Corporation, San Jose, CA (US);
Abstract
A method of fabricating structures to reduce dielectric damage due to charging is easily incorporated into existing stacked gate fabrication processes. The conductive layers are patterned to form structures which are coupled to the substrate by a current passing device. Each current passing device is isolated from the control gate structures toward the end of the etch process, thereby providing a discharge path for the control gate structures throughout substantially all of the stacked gate etch step. First and second conductive layers are patterned with one or more masks to create stacked gate structures. The multiple masks minimize the exposed area of the second conductive layer during the etch process and so reduce the amount of charging on the gate structures. Each current passing device is preferably an interconnect via coupling the second conductive layer to the first conductive layer. The discharge path allows charge to travel from the second conductive layer through the via to the first conductive layer. From the first conductive layer the charge can travel to the substrate through a buried contact structure.