Memory integrated circuit device including a memory having a

Abstract

Registers are arranged along at least opposite two sides of the four sides of a dynamic random access memory cell array. The registers are interconnected via an internal data bus line used for internal data transfer for the memory cell array. At least one register of the registers arranged along the opposite two sides is coupled with an external data bus, and the other register is coupled with an internal circuit via an internal data bus. An external controller which controls an operation in response to an external control signal is provided for the register coupled with an external circuit. An internal controller which controls an operation according to a control signal from the internal circuit is provided for the register coupled with the internal circuit. The external and internal circuits are permitted to simultaneously access the memory cell array only when the external and internal circuits read the data of a memory cell located at the same address of the memory cell array.