The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2000
Filed:
Sep. 29, 1997
Shigemichi Wakabayashi, Kanagawa-ken, JP;
Toshiyuki Oshima, Tokyo, JP;
Osamu Fuji, Tokyo, JP;
Shoichi Miyamoto, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
The present invention provides a semiconductor IC and a method for designing the same which adjusts the clock skews on a chip without additional delay circuit. A decrease in design time is realized when the semiconductor IC includes hard megacells (whose functions have been confirmed) or standard cell blocks. In the case of a semiconductor IC including hard megacells and a standard cell blocks, each megacell and standard cell block according to the present invention has sub-clock buffers on every row, for example, sub-clock buffers on the row and sub-clock buffers on the row in the megacell. The adjustment needed for accommodating clock skews on a chip is determined by calculating a delay time for the various IC chip blocks. Next, sub-clock buffers are chosen based on a result of a calculation for the delay time. Finally, the wiring design is completed which minimizes clock skew.