Method for forming contact plugs of a semiconductor device

Abstract

A method for forming contact plugs of a semiconductor device includes a step of forming a conductive layer on an insulating layer filling up a contact hole. The method further comprises a step of planarization-etching an upper surface of the insulating layer as well as the contact plugs, after formation of the contact plugs by etching the conductive layer using an etch-back or a CMP process until at least the upper surface of the insulating layer is exposed. Alternatively, the conductive and insulating layers are simultaneously planarization-etched using a CMP process once to form the contact plugs and planarize the upper surface of the insulating layer. With this method, a bridge between interconnections which can be generated due to a scratch of the upper surface of the insulating layer can be prevented by planarization-etching the conductive layer after filling up a contact hole with the conductive layer. Also, since the insulating layer includes a lower insulating layer and an upper insulating layer having a relatively high hardness to the lower insulating layer, high-step and low-step regions of the insulating layer formed along topology of a gate electrode or a metal interconnection are efficiently planarized. As a result, a thickness of the insulating layer can be considerably reduced.