The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2000

Filed:

Mar. 18, 1998
Applicant:
Inventors:

Tsung-Hsiung Wang, Ta-Li, TW;

Man-Lin Chen, Miau-Li Hsien, TW;

Chuang-Shin Chiou, Chu-Pei, TW;

Ming-Shun Chan, Hsinchu, TW;

Pei-Wen Ding, Chia-Yi, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01K / ;
U.S. Cl.
CPC ...
29852 ; 29830 ; 29832 ; 29847 ; 174261 ;
Abstract

A method for making high-density multilayer printed circuit boards is disclosed. It includes the steps of: (a) forming a pair of first conductive layers on top and bottom sides of a dielectric substrate; (b) forming first via holes through one of the first electrically conductive layers; (c) forming a blind hole through the dielectric substrate using a conformal laser drilling technique and filling the blind hole with an electrically conductive material; (d) forming a circuit pattern from the first electrically conductive layer; (e) forming a first electrically insulating layer on the first electrically conductive layer; (f) forming second via holes through the first electrically insulating layer using a non-conformal laser drilling technique; (g) forming a second electrically conductive layer covering the top surface of the circuit pattern, the first electrically insulating layer, and the side surface of the second via holes by electroplating; (h) forming a second electrically insulating layer on the first electrically conductive layer and filling the second via hole with the same electrically insulating material; (i) removing the second electrically insulating layer and the second electrically conductive layer above the second via hole; (j) forming a third electrically conductive layer on the first electrically insulating layer, wherein the third electrically conductive layer is in contact with the top edges of the second electrically conductive layer remaining on the cylindrical surface of the second via; (k) forming another circuit pattern on the third electrically conductive layer. Steps(e) through (k) can be repeated for more circuit patterns.


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