The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2000
Filed:
Jan. 26, 1998
Jin-Won Park, Choongcheongbuk-Do, KR;
LG Semicon Co., Ltd., Choongcheongbuk-Do, KR;
Abstract
A method of planarizing a multilayer semiconductor wiring structure includes the steps of forming a planarization layer on a substrate, forming a first conductive line pattern over the planarization layer, forming an insulation layer over the first conductive line pattern and the planarization layer, forming holes in the insulation layer to selectively expose portions of a top surface of the first conductive line pattern, forming a second conductive line pattern over the insulation layer, over portions of the first conductive line pattern, selectively in contact with the first conductive layer through the holes, and filling the holes, and forming a passivation layer over the second conductive line pattern, wherein conductive lines of the first conductive line pattern have a width of less than approximately 2 .mu.m.