The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2000
Filed:
Nov. 26, 1997
Applicant:
Inventors:
David Wu, San Jose, CA (US);
Scott Luning, San Francisco, CA (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438302 ; 438303 ; 438305 ;
Abstract
A CMOS semiconductor device is formed having an N-channel transistor comprising a drain region with a graded N-LDD junction. The graded N-LDD junction is obtained by plural ion implantations at different implantation dosages, energies and angles. The graded N-LDD junction reduces the electric field around the drain, thereby increasing the HCI lifetime without adversely impacting the short channel effect.
Quick Actions:
Wu, David. (2000). Method of forming semiconductor device comprising a drain region with a (U.S. Patent No. 6114210). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6114210
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile