The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2000
Filed:
Jun. 16, 1998
SpeedFam-IPEC Corporation, Chandler, AZ (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
The present invention provides methods and apparatus for optimizing the removal of thin film layers during planarization of a semiconductor wafer to achieve global uniformity of the entire semiconductor surface while further achieving the planarity within an individual die structure. A wafer polishing system suitably comprises a wafer polishing apparatus, a controller and a wafer polishing recipe. The wafer polishing recipe may be comprised of various operational parameters utilized for controlling the operation of the polishing apparatus. In a preferred embodiment, the wafer polishing apparatus is initiated with a low down force applied by a carrier apparatus and a high polishing speed applied by a polishing surface to facilitate removal of the thin film layer and optimize the planarity within a single die structure, and then followed with a high down force applied by the carrier apparatus and a low polishing speed applied by the polishing surface to facilitate removal of the thin film layer to optimize the global uniformity of the entire wafer surface. Alternatively, the low down force--high polishing speed and high down force--low polishing speed steps may be reversed without departing from the scope of the invention.