The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2000
Filed:
Apr. 22, 1998
Yasutoshi Okuno, Richardson, TX (US);
Sunil V Hattangady, McKinney, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method for forming integrated circuits having multiple gate oxide thicknesses. A high density plasma is used for selective plasma nitridation to reduce the effective gate dielectric thickness in selected areas only. In one embodiment, a pattern (12) is formed over a substrate (10) and a high density plasma nitridation is used to form a thin nitride or oxynitride layer (18) on the surface of the substrate (10) . The pattern (12) is removed and oxidation takes place. The nitride (or oxynitride) layer (18) retards oxidation (20b), whereas, in the areas (20a) where the nitride (or oxynitride) layer (18) is not present, oxidation is not retarded. In another embodiment, a thermal oxide is grown. A pattern is then placed that exposes areas where a thinner effective gate oxide is desired. The high density plasma nitridation is performed converting a portion of the gate oxide to nitride or oxynitride. The effective thickness of the combined gate dielectric is reduced.