The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2000
Filed:
Oct. 30, 1997
Peter Heinrich, Rosenheim, DE;
STMicroelectronics GmbH, Grasbrunnm, DE;
Abstract
A device for selection of address words, each having n bit locations and serving for addressing m different receiving locations of a digital communications apparatus, comprising a digital acceptance device via which address words can be selected which are acceptable for the particular receiving location in consideration. The acceptance device includes an address word segmenting device through which each address word received by the receiving location is subdivided into s address word segments with b segment bit locations each, wherein b=n/s and n is an integral multiple of s, a decoder having a decoder input accepting the bit pattern of the address word segment of the particular address word being examined for acceptance, and having a decoder output at which, for each of the possible segment bit patterns, a decoder output bit pattern representing only this segment bit pattern is available. The device also includes s filter registers associated with one of the address word segments each, for storing filter register bit patterns, a comparison circuit through which the decoder output bit pattern can be compared with the contents of the associated filter register, the output providing an examination result signal which is either a conformity signal or a non-conformity signal. The device also includes an evaluation circuit, that delivers an acceptance signal only when a conformity signal has been present at the output of the comparison circuit for each address word segment of this address word.