The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2000

Filed:

Jul. 31, 1998
Applicant:
Inventors:

Dan Ion Hariton, Pinole, CA (US);

Ronald Pasqualini, Los Altos, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H / ;
U.S. Cl.
CPC ...
361111 ; 361 56 ; 361 58 ; 361118 ;
Abstract

An electrostatic discharge (ESD) protection circuit includes circuitry for providing protection against ESD events which occur either within an ESD pad ring (intra-ring) or between different ESD pad rings (inter-ring). Self-triggering voltage clamp circuits or back-to-back diode circuits can be used to properly interconnect the positive polarity rails and the negative polarity rails of the ESD pad rings. Self-triggering voltage clamp circuits are advantageous in that they provide improved ac signal isolation (i.e. reduced noise coupling between the ESD pad rings, and thus reduced noise coupling from the digital I/O pads to the analog I/O pads).


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