Memory block for realizing semiconductor memory devices and

Abstract

An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks. Also provided is a method of implementing the memory block, as organized into a matrix-like configuration, individually selectable from a plurality of blocks embedded in a memory device, wherein each memory cell is identified by a continuous bit line enabled by at least one block selector, by a broken bit line or `segment` connected to the continuous one through an address device, and by a word line orthogonal to the direction of the bit lines, and formed on a substrate having a first type of conductivity.