The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2000
Filed:
Nov. 03, 1999
Jeffrey C Kalb, Saratoga, CA (US);
John Jorgensen, Los Gatos, CA (US);
Jeffrey C Kalb, Jr, Phoenix, AZ (US);
Dominick Richiuso, Saratoga, CA (US);
California Micro Devices Corporation, Milpitas, CA (US);
Abstract
An active termination circuit for terminating a transmission line in memory bus, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor. The first threshold reference device being configured to maintain a base of the first clamping transistor at about V.sub.BE lower than the second reference voltage level. There is further included a second threshold reference device coupled to the second clamping transistor, the second threshold reference device being configured to maintain a base of the second clamping transistor at about V.sub.BE higher than the first reference voltage level.