The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2000
Filed:
Aug. 20, 1997
Applicant:
Inventors:
Bin Zhao, Irvine, CA (US);
Prahalad K Vasudev, Austin, TX (US);
Ronald S Horwath, Santa Clara, CA (US);
Thomas E Seidel, Sunnyvale, CA (US);
Peter M Zeitzoff, Austin, TX (US);
Assignees:
Sematech, Inc., Austin, TX (US);
Lucent Technologies Inc., Murray Hill, NJ (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438638 ; 438622 ; 438623 ; 438627 ; 438643 ; 438636 ; 438637 ; 438638 ; 438648 ; 438653 ; 438656 ; 438672 ; 438685 ; 438687 ; 438902 ;
Abstract
A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.di-elect cons.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.di-elect cons. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.