The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2000
Filed:
May. 03, 1999
Kazuya Mori, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A memory cell array architecture (300) for memory cells having a 6F.sup.2 area, where F is a minimum feature size, is disclosed. The array architecture (300) includes active areas (302a-302n) arranged into even columns and odd columns. The active areas (302a-302n) each include a central portion (306) and are separated from one another within a column by column spacing structures (308). The active areas of even columns are offset from those of odd columns so that the central portion the even column active areas are aligned, in the row direction, with the column spacing structures of the odd columns. This arrangement allows bit line contacts (312a-312g) to be formed at the central portions with less restrictive alignment constraints. Two storage node contacts (316a-316t) are also formed to each active area (302a-302n). A novel lithography mask for improved creation of the storage node contacts is also disclosed.