The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2000

Filed:

Sep. 02, 1998
Applicant:
Inventors:

Young Hoon Lee, Somers, NY (US);

Ying Zhang, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438700 ; 438702 ; 438753 ;
Abstract

In a dual-damascene processes for multi level interconnection a method for forming trenches and vias in the inter-insulation is accomplished without etching out the inter-insulation layer. A thick sacrificial layer is first deposited and reversed etched to form sacrificial pillars 64 forming the vias and sacrificial bridges 72 forming the trenches. The sacrificial layer can be any material (insulator, semiconductor, or metal), provided it can be easily patterned and selectively removed later over the inter insulator layer. Thereafter a low-k inter-insulation layer is deposited around the sacrificial pillars and bridges. It is these sacrificial pillars and bridges that are etched away leaving behind vias and trenches in the inter-insulation layer. An advantage of the invention is that it replaces a difficult RIE process of vias and trenches with a much easier RIE of sacrificial pillars and bridges. In the preferred embodiment, a silicon film, either amorphous or polycrystalline, is used as the sacrificial layer.


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