Fabrication of a non-ldd graded p-channel mosfet

Abstract

A transistor and transistor fabrication method are presented in which a graded junction is formed using a plurality of source/drain dopant implants. The implants are performed such that higher concentrations of dopant species are implanted at lower energies and lower dopant concentrations are implanted at higher energies. In an embodiment, an anneal step is used to create the graded junction by exploiting the concentration dependence of the dopant diffusivity (i.e., dopant species implanted in regions of high concentration are more mobile than dopant species implanted in regions of low concentration). Sub-0.25-micron transistors formed by the process described herein may be less susceptible to deleterious capacitive loading and parasitic resistance than transistors having conventionally formed lightly doped drain and source/drain implants. Transistors formed according to the method of this application may also advantageously include highly doped shallow junctions while incorporating lightly doped deeper junctions to avoid the problem of junction spiking. Integrated circuits including transistors formed according to the method described herein may further be subject to less inter-transistor variation in effective channel length, and therefore threshold voltage roll-off and drive current variability, than integrated circuits including conventionally formed transistors.