The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2000
Filed:
Jul. 24, 1998
Osamu Yamada, Tokorozawa, JP;
Koji Hara, Fujisawa, JP;
Advantest Corp., Tokyo, JP;
Abstract
A test pattern generation apparatus and method for an SDRAM can easily generate a test pattern for a synchronous dynamic RAM (SDRAM) by having a specific wrap conversion circuit or an address conversion method. The wrap conversion circuit is provided to receive two types of address data from a pattern generator and converts the data through a specified logic circuit information. The test pattern generation method for the SDRAM is carried out by inputting column address data and wrap address data, and by generating output data which has been converted by a predetermined logic equation. The test pattern generation apparatus and method can also include an address inversion scramble for the converted output.