The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2000

Filed:

Mar. 20, 1998
Applicant:
Inventors:

Ramnath Venkatraman, Austin, TX (US);

John Mendonca, Austin, TX (US);

Gregory N Hamilton, Pflugerville, TX (US);

Jeffrey T Wetzel, Austin, TX (US);

Tze W Poon, Sunnyvale, CA (US);

Sam S Garcia, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257751 ; 257740 ; 257741 ; 257750 ; 257757 ; 257762 ; 257768 ; 438595 ; 438627 ; 438643 ; 438653 ; 438682 ; 438687 ;
Abstract

A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier layer is formed on the insulating layer and in the opening by providing a plurality of refractory metal atoms and a plurality of silicon atoms in the processing chamber. The atoms are ionized by applying a first bias to the atoms to form a plasma. The substrate is then biased by a first stage bias followed by a second stage bias to accelerate the plasma to the substrate to form the copper barrier layer, where the first stage bias is less than the second stage bias. The copper-containing metal is then deposited on the copper barrier layer over the insulating layer and in the opening. The present invention further includes a semiconductor device formed by the above method.


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