Method of making pseudomorphic high electron mobility transistors

Abstract

A method for forming a gate of a field effect transistor wherein a structure is provided having: a gallium arsenide substrate; an indium gallium arsenide channel layer over the substrate; a doped aluminum gallium arsenide barrier layer over the channel layer; a gallium arsenide protective layer disposed on the donor layer; an indium gallium phosphide etch stop layer disposed over the protective layer; and a gallium arsenide source and drain contact layer disposed over the etch stop layer. A mask is provided over the surface of the structure to expose a surface portion of the contact layer. The exposed surface portion of the contact layer is subjected to a first etch and etching through the contact layer to expose an underlying surface portion of the etch stop layer. The first etch etches the contact layer at a substantially greater etch rate than the etch rate of such etch to the etch stop layer. The exposed surface portion of the etch stop layer is then subjected to a second etch and etching through the etch stop layer to expose an underlying surface portion of the protective layer. The second etch etches the etch stop layer at a substantially greater etch rate than the etch rate of such second etch to the protective layer. A gate metal is deposited over the mask and through etched portions of the etch stop layer onto, and in Schottky contact with the exposed portion of the protective layer. The method allows the formation of a gate recess by selective wet etching thereby eliminating surface damage associated with a dry etch and ungated recess. Because of the wet etching selectivity measurement of the channel current is eliminated to determine the etching end point.