Pulse discriminating clock synchronizer for logic derived clock signals

Abstract

A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuitry for synchronizing the asynchronous logic derived clock signal to be a reference clock signal is coupled to the circuitry for generating. The circuitry for synchronizing generates a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal but only when the input signals are recognized as clocking signals. That is, the synchronizing circuitry discriminates between valid input signals and spurious signals or noise. Further, the programmable device includes circuitry for suspending a clock signal. In one embodiment, input signal having at least a minimum duration is received and used to generate an asynchronous logic derived clock signal. The asynchronous logic derived clock signal is synchronized with a synchronous clock signal provided to the programmable device to produce a synchronous logic derived clock signal. The asynchronous logic derived clock signal is logically combined with the synchronized logic derived clock signal to produce a suspended clock signal.