The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2000
Filed:
Dec. 31, 1997
Zelig Wayner, Haifa, IL;
Intel Corporation, Santa Clara, CA (US);
Abstract
An input buffer to interface between a main logic circuit and a peripheral device, which includes a first transistor that is adapted to be coupled to a first voltage supply and a first terminal, is described. A second transistor, which is adapted to be coupled to a second voltage supply and said terminal, is also included. The input buffer includes a first logic circuit to limit the amount of voltage applied to the first and second enable terminals of the first and second transistors. The first logic circuit is adapted to be coupled to a second terminal, the first enable terminal, and the second enable terminal. A second logic circuit, designed to limit the amount of voltage applied to the first terminal, is also included. The second logic circuit is coupled to the input terminals of the first and second transistors, as well as the first terminal. A method for buffering a signal received from a peripheral component includes receiving a first signal from a peripheral component. The voltage level of the first signal is reduced, and it is applied to the enable terminals of a first and a second transistor. A second signal is applied to an output terminal, and the voltage level of the second signal is limited. The second signal is then transmitted to an internal component.