The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2000

Filed:

Jun. 22, 1999
Applicant:
Inventor:

Raj Nair, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F / ;
U.S. Cl.
CPC ...
323273 ; 323280 ;
Abstract

A voltage regulator that has a first mode circuit having a gating device and an amplifier, the gating device with a first input for receiving a first voltage, a second input, and an output. The amplifier is configured to receive a reference voltage and the gating device output as the second input. The gating device is configured to receive an amplifier output at said second input and responsive thereto to couple the first voltage with the gating device output when the gating device output is within a voltage range. The voltage regulator also has a second mode circuit having a voltage divider with an output. The voltage divider is configured to received the first voltage and supply a second voltage to the voltage divider output. The invention also relates to an integrated circuit having a power bus line and at least two voltage regulator cells coupled to the power bus line.


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Nair, Raj. (2000). System and method for multi-mode low power voltage regulator (U.S. Patent No. 6084385). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6084385

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