The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2000
Filed:
May. 01, 1998
Allen Flanigan, San Jose, CA (US);
Michael N Sugarman, San Francisco, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Apparatus for biasing and retaining a wafer in a semiconductor wafer processing system. The apparatus has a pedestal, a puck and an electrode disposed between the pedestal and the puck. The pedestal defines an enclosure within which the electrode and other pedestal components are housed. The electrode may serve as a cooling plate for the puck. Each of the components is insulated so as to define an electrical path. The electrical path consists of a conductor connected to a coolant tube inside the enclosure and the cooling plate which is in contact with the coolant tube. The cooling plate is electrically isolated from the pedestal via an isolator ring that circumscribes an upper inner wall of the enclosure. The coolant tube is disposed in a channel on the bottomside of the cooling plate and affixed to the plate so as to establish physical contact. The coolant tube and plate conduct RF power from a power source connected to the tube. The power then capacitively couples through the electrostatic chuck to bias a wafer retained thereon. The cooling plate also provides for temperature control of the wafer via a plurality of grooves on the top surface of the plate.