Integrated placement and synthesis for timing closure of microprocessors

Abstract

One aspect of the invention relates to a method for improving timing convergence in computer aided semiconductor circuit design. In one particular version of the invention, the method includes the steps of generating a behavioral model of a desired semiconductor circuit, which includes timing constraints for individual paths in the circuit, synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, and the step of synthesizing includes performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets. Next, the components in the netlist are placed into an image representing a predefined area of the semiconductor chip. During this step, actual wire lengths are determined for the nets in the netlist. The steps of synthesizing and placing are then repeated until timing convergences is achieved. Each time the step of synthesizing is repeated, the actual wire lengths from the step of placing are substituted for the estimated wire lengths. Finally, the circuit is routed to produce the final design data.