Data enabled logic circuits

Abstract

Data enabled complex logic gates provide improved speed/power performance over conventional topologies such as static logic or clocked domino logic. Within a data enabled complex logic gate, complementary parallel logic structures, such as NFET logic trees, are configured such that for any combination of input variables one logic structure will produce a logic low as an output and the other logic structure will produce a logic high as an output. The logic structures are cross-coupled to each other by way of internal precharge devices, and are further individually coupled to an output latch. In this way the logic structures can be precharged to prepare for evaluation of the next set of input signals while the output latch maintains the result of the previous evaluation. In a further aspect of the invention, data enabled complex logic gates are combined with pass gate latches and multiplexer based logic gates to produce a high-speed, low-power logic pipeline.