The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2000
Filed:
Jun. 25, 1997
Applicant:
Inventor:
Ramesh Panwar, Santa Clara, CA (US);
Assignee:
Sun Microsystems, Inc., Palo Alto, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
39550002 ;
Abstract
A system and method for efficient implementation of a multi-port logic first-in, first-out ('FIFO') structure or particular utility in high clock speed integrated circuit ('IC') processor design which provides for reduced on-chip area requirements and fewer and less timing critical electrical interconnect paths. The advantageous reduction in IC area and enhanced performance disclosed herein is enabled through the rotation of the inputs and outputs of the FIFO; maintenance of decoded head and tail pointers, and folding the FIFO entry locations such that the entries are arranged in an interleaved fashion.