High-speed static random access memory

Abstract

A semiconductor memory has a plurality of word lines a plurality of bit line pairs and a plurality of memory cells formed at intersection points between the word lines and the bit line pairs. A word decoder generates a word line select signal upon receipt of an address signal and a bit decoder generates a bit line select signal on receiving the address signal. A bit line load circuit receives a signal current from the applicable memory cell, a sense circuit detects an output signal from the bit line load circuit, and a bit line pull-down circuit and a bit line recovery circuit drives the applicable bit lines upon writing data to the memory cell in question. The bit line load circuit and the bit line recovery circuit include pMOS transistors whose drains are connected to the bit lines and whose gates are fed with a control signal, and diodes whose anodes are connected to a first power supply and whose cathodes are connected to sources of the pMOS transistors, the pMOS transistors and the diodes being furnished to each of the bit line pairs. The pMOS transistors are inhibited from conducting while the bit lines are being driven Low by the bit line pull-down circuit during a write cycle, and allowed to conduct during other periods including a read cycle. This constitution shortens the recovery time, implementing a high-speed SRAM with a shortened cycle time.