The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2000
Filed:
Feb. 08, 1999
Kuen-Yow Lin, Chia-I, TW;
Kuo-Chi Lin, Lu-Chou, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A method for forming different area vias of dynamic random access memory is disclosed. Essential points of the invention comprise spacer is only formed on gate of periphery circuit, and depth of passivation layer of periphery circuit gates is larger than depth of layer that capped over gates of cell. The provided method comprises following steps: First, capping a layer over gate of cell and gate of periphery circuit and then forming spacer on gate of periphery circuit, where depth of capping layer is smaller than depth of passivation layer of periphery circuit gate. Second, both gate of cell and gate of periphery circuit are cover by a dielectric layer. Third, vias in both cell and periphery circuit are formed simultaneously by photolithography and etching, where etching comprises etching of dielectric layer and etching of passivation layer. Advantageous of the invention is only a photolithography process is necessary and then throughput is enhanced.