The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2000

Filed:

Jun. 16, 1998
Applicant:
Inventors:

Rajesh Rengarajan, Poughkeepsie, NY (US);

Hirofumi Inoue, Fishkill, NY (US);

Radhika Srinivasan, Mahwah, NJ (US);

Jochen Beintner, Wappingers Falls, NY (US);

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438218 ; 438400 ; 438424 ;
Abstract

A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.


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